A Cost Effective ATE Calibration / Verification Solution by Edgar

This thesis describes the SD-34 system verification ASIC that will provide a cost efficient solution in calibrating/verifying ATE systems when testing high-speed memory devices. The heart of the ASIC is a High Resolution Skew Detector (HRSD) which converts in-phase as well as out-of-phase skew into a usable signal for use off-chip using a novel time-to-voltage conversion (TVC) technique. Multiple target signals are compared to a reference signal one at a time with the use of an analog multiplexer. The HRSD suffers from relatively little metastable jitter problems as compared to many other conventional phase/skew detection circuits. Overall theoretical performance is estimated to have subpicosecond resolution and a few picoseconds linearity. The ASIC will be used in an array configured on the test head such that parallelism can be added to the system verification process. This will reduce costs due to production time and may offer a superior solution for AC calibration due to its Device Under Test (DUT) level testing capability. The process used to fabricate this ASIC is Austria Mikrosysteme's 0.8gm BiCMOS process technology. Thesis Supervisor: Anantha Chandrakasan Title: Associate Professor, MIT Microsystems Technology Laboratories